Design and throughput simulations of a hard x-ray split and delay line for the MID station at the European XFEL

This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. This article appeared in AIP Conference Proceedings 1741, 030010 (2016) and may be found at https://doi.org/10.1063/1.4952833.A hard X-ray Split and Delay Line (SDL) under development for the Materials Imaging and Dynamics (MID) station at the European X-Ray Free-Electron Laser (XFEL.EU) is presented. This device will provide pairs of X-ray pulses with a variable time delay ranging from −10 ps to 800 ps in a photon energy range from 5 to 10 keV. Throughput simulations in the SASE case indicate a total transmission of 1.1% or 3.5% depending on the operation mode. In the self-seeded case of XFEL.EU operation simulations indicate that the transmission can be improved to more than 11%.BMBF, 05K13KT4, Verbundprojekt FSP 302 - Freie-Elektronen-Laser: Nanoskopische Systeme. Teilprojekt 1: Split-and-Delay Instrument für die European XFEL Beamline Materials Imaging and Dynamic

Power estimation on functional level for programmable processors

In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW)-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA). Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%.</p><p style=&quot;line-height: 20px;&quot;> In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW) -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA). This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated the input parameters of the Correspondence to: H. Blume ([email protected]) arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. This approach is exemplarily demonstrated and evaluated applying two modern digital signal processors and a variety of basic algorithms of digital signal processing. The resulting estimation values for the inspected algorithms are compared to physically measured values. A resulting maximum estimation error of 3% is achieved

Probabilistic modeling of noise transfer characteristics in digital circuits

Device scaling, the driving force of CMOS technology, led to continuous decrease in the energy level representing logic states. The resulting small noise margins in combination with increasing problems regarding the supply voltage stability and process variability creates a design conflict between efficiency and reliability. This conflict is expected to rise more in future technologies. Current research approaches on fault-tolerance architectures and countermeasures at circuit level, unfortunately, cause a significant area and energy penalty without guaranteeing absence of errors. To overcome this problem, it seems to be attractive to tolerate bit errors at circuit level and employ error handling methods at higher system levels. To do this, an estimate of the bit error rate (BER) at circuit level is necessary. Due to the size of the circuits, Monte Carlo simulation suffers from impractical runtimes. Therefore the needed modeling scheme is proposed. The model allows a probabilistic estimation of error rates at circuit level taking into account statistical effects ranging from supply noise and electromagnetic coupling to process variability within reasonable runtimes

Implementation of the Hydrographic Data Acquisition and Processing System (HDAPS) in the NOAA Fleet

The U.S. National Oceanic and Atmospheric Administration (NOAA) has developed an automated system for acquiring and processing hydrographic field data in support of its charting mission. The Hydrographic Data Acquisition and Processing System (HDAPS) addresses NOAA’s broad requirement to conduct hydrographic surveys in the coastal waters of the U.S. Systems have been successfully deployed on ships, launches, and small boats. Two types of HDAPS data acquisition systems (DAS) are presented. The first system, based on Hewlett-Packard (HP) hardware, is deployed on ships and launches. The second type is a small boat, 24-volt system, based on 1BM-PC compatible hardware. Both types of DAS are capable of conducting echo sounding and side scan sonar surveys. Data acquired by both systems are processed on an HP-based data processing system

Quantitative design space exploration of routing-switches for Network-on-Chip

Future Systems-on-Chip (SoC) will consist of many embedded functional units like e.g. embedded processor cores, memories or FPGA like structures. These SoCs will have huge communication demands, which can not be fulfilled by bus-based communication systems. Possible solutions to this problem are so called Networks-on-Chip (NoC). &lt;br&gt;&lt;br&gt; These NoCs basically consist of network-interfaces which integrate functional units into the NoC and routing-switches which connect the network-interfaces. Here, VLSI-based routing-switch implementations are presented. The characteristics of these NoCs like performance and costs (e.g. silicon area respectively logic elements, power dissipation) depend on a variety of parameters. As a routing-switch is a key component of a NoC, the costs and performance of routing-switches are compared for different parameter combinations. Evaluated parameters are for example data word length, architecture of the routing-switch (parallel vs. centralized implementation) and routing-algorithm. &lt;br&gt;&lt;br&gt; The performance and costs of routing-switches were evaluated using an FPGA-based NoC-emulator. In addition different routing-switches were implemented using a 90 nm standard-cell library to determine the maximum clock frequency, power-dissipation and area of a VLSI-implementation. The power consumption was determined by simulating the extracted layout of the routing-switches. Finally, these results are benchmarked to other routing-switch implementations like Aetheral and xpipes

Local regulation of the coronary circulation in health and disease: role of nitric oxide and endothelin

Coronary artery disease is the leading cause of morbidity and mortality in western countries. Its pathogenesis is unknown, but involves enhanced vasoconstriction, increased interaction of platelets and monocytes with the vessel wall, as well as proliferation, migration and extracellular matrix formation of vascular smooth muscle. The endothelium lies in a strategic anatomical position between circulating blood and vascular smooth muscle cells. This supports the concept that dysfunction of these cells significantly contributes to coronary artery disease. Besides other mediators, endothelial cells are a source of nitric oxide and endothelin. Nitric oxide is a vasodilator, an inhibitor of both platelet function and proliferation and migration of vascular smooth muscle. Endothelin is a potent vasoconstrictor that facilitates proliferation. Under pathological conditions, in particular the presence of cardiovascular risk factors, endothelial dysfunction occurs and is a major contributor to the increase in platelet vessel wall interaction, vasoconstriction and proliferation in the coronary system. Endothelium-dependent vasodilation is usually reduced and endothelium-dependent constrictor responses, as well as endothelin production, are augmented. Hence, endothelial cells are important targets and mediators of coronary artery diseas

A low power clock generator with adaptive inter-phase charge balancing for variability compensation in 40-nm CMOS

Power dissipation besides chip area is still one main optimization issue in high performance CMOS design. Regarding high throughput building blocks for digital signal processing architectures which are optimized down to the physical level a complementary two-phase clocking scheme (CTPC) is often advantageous concerning ATE-efficiency. The clock system dissipates a significant part of overall power up to more than 50% in some applications. <br><br> One efficient power saving strategy for CTPC signal generation is the charge balancing technique. To achieve high efficiency with this approach a careful optimization of timing relations within the control is inevitable. <br><br> However, as in modern CMOS processes device variations increase, timing relations between sensitive control signals can be affected seriously. In order to compensate for the influence of global and local variations in this work, an adaptive control system for charge balancing in a CTPC generator is presented. An adjustment for the degree of charge recycling is performed in each clock cycle. In the case of insufficient recycling the delay elements which define duration and timing position of the recycling pulse are corrected by switchable timing units. <br><br> In a benchmark with the conventional clock generation system, a power reduction gain of up to 24.7% could be achieved. This means saving in power of more than 12% for a complete number-crunching building block

Development of a hard X-ray split-and-delay line and performance simulations for two-color pump-probe experiments at the European XFEL

This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. This article appeared in Review of Scientific Instruments 89, 063121 (2018) and may be found at https://doi.org/10.1063/1.5027071.A hard X-ray Split-and-Delay Line (SDL) under construction for the Materials Imaging and Dynamics station at the European X-Ray Free-Electron Laser (XFEL) is presented. This device aims at providing pairs of X-ray pulses with a variable time delay ranging from −10 ps to 800 ps in a photon energy range from 5 to 10 keV for photon correlation and X-ray pump-probe experiments. A custom designed mechanical motion system including active feedback control ensures that the high demands for stability and accuracy can be met and the design goals achieved. Using special radiation configurations of the European XFEL’s SASE-2 undulator (SASE: Self-Amplified Spontaneous Emission), two-color hard x-ray pump-probe schemes with varying photon energy separations have been proposed. Simulations indicate that more than 109 photons on the sample per pulse-pair and up to about 10% photon energy separation can be achieved in the hard X-ray region using the SDL.BMBF, 05K13KT4, Verbundprojekt FSP 302 - Freie-Elektronen-Laser: Nanoskopische Systeme. Teilprojekt 1: Split-and-Delay Instrument für die European XFEL Beamline Materials Imaging and DynamicsBMBF, 05K16BC1, Split-and-Delay Instrument für die European XFEL Beamline Materials Imaging and Dynamic